-----------------------------------------------
-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/02/2007
-----------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

-- LFSR 1-bit block
ENTITY one_bit_block IS
	PORT (	xor_in0			: IN  STD_LOGIC;	-- XOR input from feedback line	
			mux_sel			: IN  STD_LOGIC;	-- Multiplexer select
			flop_in			: IN  STD_LOGIC;	-- D flop input
			flop_clock		: IN  STD_LOGIC;	-- PosEdge Clock used	
			flop_reset		: IN  STD_LOGIC;	-- Resets the flop to 0, active HIGH
			flop_set		: IN  STD_LOGIC;	-- Sets the flop to 1, active HIGH
			lfsr_out		: OUT STD_LOGIC; 	-- Output as an LFSR output bit
      		output_next		: OUT STD_LOGIC 	-- Output: input to next stage
			);
END one_bit_block;

ARCHITECTURE struct OF one_bit_block IS
	COMPONENT mux21
		PORT (	in0,in1			: IN  STD_LOGIC;	-- Multiplexer inputs	
				sel				: IN  STD_LOGIC;	-- Multiplexer select
	      		q_m	 			: OUT STD_LOGIC 	-- Multiplexer output
				);
	END COMPONENT;
	
	COMPONENT dflop IS
		PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
				reset			: IN  STD_LOGIC;	-- Resets the flop to 0, active HIGH
				set				: IN  STD_LOGIC;	-- Sets the flop to 1, active HIGH
				input			: IN  STD_LOGIC;	-- Flop input
	      		q	 			: OUT STD_LOGIC 	-- Flop output
				);	
	END COMPONENT;
	
	SIGNAL flop_q, xor_out : STD_LOGIC;
	
BEGIN
	xor_out <= flop_q XOR xor_in0;
	U00: mux21_1bit PORT MAP (in0 => flop_q, in1 => xor_out, sel => mux_sel, q_m => output_next);
	U01: dflop PORT MAP (clock => flop_clock, reset => flop_reset, set => flop_set, input => flop_in, q => flop_q);
	lfsr_out <= flop_q;
END struct;